Computer Architecture & Microprocessors
What your code actually runs on.
CPU Anatomy: ALU, Registers, Control Unit, Datapath
A CPU core is a symphony of specialized circuits — registers hold the notes, the ALU plays them, the control unit conducts, and the datapath is the stage they all share.
ISAs: RISC vs CISC, x86 / ARM / RISC-V
An ISA is the contract between software and silicon — understanding RISC vs CISC, x86/ARM/RISC-V trade-offs, and why the kernel must speak every dialect is the foundation of everything low-level.
The Fetch-Decode-Execute Cycle
The fetch-decode-execute cycle is the heartbeat of every CPU — master this loop and you understand the substrate on which the entire Linux kernel runs.
Pipelining
Pipelining is the assembly-line trick that lets a CPU start a new instruction every clock cycle by overlapping the five stages of instruction execution across multiple instructions simultaneously.
Hazards & Branch Prediction
Hazards are the price of pipelining; branch prediction is the hardware's educated gamble to keep paying it as rarely as possible.
Superscalar, Out-of-Order & Speculative Execution
Modern CPUs execute dozens of instructions simultaneously by renaming registers, reordering operations, and betting on the future — all while appearing perfectly sequential to your program.
Caches Deep Dive: Associativity & Coherence
Caches are the single biggest lever between your code's theoretical speed and what the hardware actually delivers — mastering them is mastering modern systems.
Virtual Memory, the MMU, TLB & Paging
Virtual memory is the hardware-enforced illusion that every process owns all of memory — understanding it means understanding isolation, performance, and the entire Linux MM subsystem.
Privilege Levels, Protection Rings & CPU Modes
The CPU itself decides who to trust — privilege rings are not an OS policy but a silicon guarantee, and every system call is a tightly controlled leap across that boundary.
Interrupts, Exceptions & Traps
Interrupts are the nervous system of a computer — this module explains exactly how hardware events hijack the CPU, save its soul, and hand control to the kernel.
I/O: MMIO, Port I/O, DMA & Buses (PCIe)
From the humble IN instruction to multi-gigabyte DMA rings and MSI-X vectors: every mechanism that lets a CPU talk to real hardware, made rigorous.
Multicore, SMP, NUMA & Memory Models
From bare silicon to lock-free algorithms: how multiple cores share memory without chaos, and the formal rules every kernel developer must internalize to write correct concurrent code.